Adaptive Operation of 3D NAND Memory

ABSTRACT

In a nonvolatile memory block that contains separately-selectable sets of NAND strings, a bit line current sensing unit is configured to sense bit line current for a separately-selectable set of NAND strings of the block. A bit line voltage adjustment unit is configured to apply a first and second bit line voltages to separately-selectable sets of NAND strings that have bit line currents greater and less than the minimum current respectively, the second bit line voltage being greater than the first bit line voltage.

CROSS-REFERENCED APPLICATION

This application is a continuation of U.S. application Ser. No.14/861,951 filed Sep. 22, 2015, which is herein incorporated in itsentirety by this reference.

BACKGROUND

This application relates to the operation of re-programmable nonvolatilememory such as semiconductor flash memory.

Solid-state memory capable of nonvolatile storage of charge,particularly in the form of EEPROM and flash EEPROM packaged as a smallform factor card, has become the storage of choice in a variety ofmobile and handheld devices, notably information appliances and consumerelectronics products. Unlike RAM (random access memory) that is alsosolid-state memory, flash memory is non-volatile, and retains its storeddata even after power is turned off. Also, unlike ROM (read onlymemory), flash memory is rewritable similar to a disk storage device.

Flash EEPROM is similar to EEPROM (electrically erasable andprogrammable read-only memory) in that it is a non-volatile memory thatcan be erased and have new data written or “programmed” into theirmemory cells. Both utilize a floating (unconnected) conductive gate, ina field effect transistor structure, positioned over a channel region ina semiconductor substrate, between source and drain regions. A controlgate is then provided over the floating gate. The threshold voltagecharacteristic of the transistor is controlled by the amount of chargethat is retained on the floating gate. That is, for a given level ofcharge on the floating gate, there is a corresponding voltage(threshold) to be applied to the control gate before the transistor isturned “on” to permit conduction between its source and drain regions.Flash memory such as Flash EEPROM allows entire blocks of memory cellsto be erased at the same time.

The floating gate can hold a range of charges and therefore can beprogrammed to any threshold voltage level within a threshold voltagewindow. The size of the threshold voltage window is delimited by theminimum and maximum threshold levels of the device, which in turncorrespond to the range of the charges that can be programmed onto thefloating gate. The threshold window generally depends on the memorydevice's characteristics, operating conditions and history. Eachdistinct, resolvable threshold voltage level range within the windowmay, in principle, be used to designate a definite memory state of thecell.

Nonvolatile memory devices are also manufactured from memory cells witha dielectric layer for storing charge. Instead of the conductivefloating gate elements described earlier, a dielectric layer is used. AnONO dielectric layer extends across the channel between source and draindiffusions. The charge for one data bit is localized in the dielectriclayer adjacent to the drain, and the charge for the other data bit islocalized in the dielectric layer adjacent to the source. Multi-statedata storage is implemented by separately reading the binary states ofthe spatially separated charge storage regions within the dielectric.

Many nonvolatile memories are formed along a surface of a substrate(e.g. silicon substrate) as two dimensional (2D), or planar, memories.Other nonvolatile memories are three dimensional (3-D) memories that aremonolithically formed in one or more physical levels of memory cellshaving active areas disposed above a substrate.

SUMMARY

A block in a three-dimensional nonvolatile memory may include multipleseparately-selectable sets of NAND strings some of which may havecharacteristics that are outside the normal range of characteristics forNAND strings, which may cause them to fail at some point, either duringtesting or during operation. For example, an erase fail may occurbecause current flow through a separately-selectable set of NAND stringsduring erase-verify is low as a result of a resistance in series witherased memory cells. Such a resistance may be, for example, due to apoor connection between the NAND string and a bit line, or between theNAND string and a common source, or may be due to one or more selecttransistors, or some other element. Low current due to such a resistancemay be overcome by applying a higher bit line voltage. This can be doneon a string by string basis, column by column basis (where a columnincludes multiple bit lines), or for a whole separately-selectable setof NAND strings. A record may be maintained to indicate bit linevoltages to use. Low current caused by select transistors may be broughtto an acceptable level by applying increased select line voltage. Datastored in portions of a block that require modified parameters such asincreased bit line or select line voltages may be stored with anincreased redundancy ratio to ensure that data is safely maintained.

An example of a three dimensional nonvolatile memory system includes: ablock that contains a plurality of separately-selectable sets of NANDstrings; a bit line current sensing unit that is configured to sense bitline current for a separately-selectable set of NAND strings of theblock and to compare the bit line current to a minimum current; and abit line voltage adjustment unit that is in communication with the bitline current sensing unit, the bit line voltage adjustment unitconfigured to apply a first bit line voltage to separately-selectablesets of NAND strings that have bit line currents greater than theminimum current, and configured to apply a second bit line voltage toseparately-selectable sets of NAND strings that have bit line currentsless than the minimum current, the second bit line voltage being greaterthan the first bit line voltage.

The first and second bit line voltages may be applied duringprogramming, reading, or erasing of the block. The bit line currentsensing unit may be configured to sense bit line current for each of theplurality of separately-selectable sets of NAND strings of the block andto compare each of the bit line currents with the minimum current, andthe bit line voltage adjustment unit may be configured to apply at leastthe second bit line voltage to any of the plurality ofseparately-selectable sets of NAND strings in the block that have bitline currents that are less than the minimum current. A table may recordan entry for each separately-selectable set of NAND strings thatreceives at least the second bit line voltage, an entry indicating a bitline voltage to be applied to a corresponding separately-selectable setof NAND strings. A select line voltage sensing unit may be configured tosense select line threshold voltage and to compare a select linethreshold voltage with a minimum threshold voltage; and a select linevoltage adjustment unit may be configured to adjust select line voltagefor a select line that has a select line threshold voltage that is lessthan the minimum threshold voltage. A table may record an entry for eachseparately-selectable set of NAND strings that has a select linethreshold voltage that is less than the minimum threshold voltage, anentry in the table indicating a select line voltage to be applied to aselect line in a corresponding separately-selectable set of NANDstrings. An adaptive data encoding unit may encode data with variableredundancy prior to storage, the adaptive data encoding unit may beconfigured to apply a first redundancy scheme to data stored inseparately-selectable sets of NAND strings that have bit line currentsgreater than the minimum current, and configured to apply a secondredundancy scheme to data stored in separately-selectable sets of NANDstrings that have bit line currents less than the minimum current. Atable may record an entry for each separately-selectable set of NANDstrings that has bit line currents less than the minimum current, anentry in the table indicating a redundancy scheme to be applied to datastored in a corresponding separately-selectable set of NAND strings.

An example of a three dimensional nonvolatile memory includes: a firstseparately-selectable set of NAND strings in a block, data in the firstseparately-selectable set of NAND strings encoded with a first level ofredundancy; and a second separately-selectable set of NAND strings inthe block, data in the second separately-selectable set of NAND stringsencoded with a second level of redundancy that provides a higher levelof error correction capability than the first level of redundancy.

An adaptive encoder/decoder may be configured to encode and decode datawith a variable level of redundancy according to characteristics ofseparately-selectable sets of NAND strings in which data is stored. Abit line adjustment unit may be configured to apply a first bit linevoltage to bit lines in the first separately-selectable set of NANDstrings and to apply a second bit line voltage to bit lines in thesecond separately-selectable set of NAND strings. Configuration of theadaptive encoder/decoder, and configuration of the bit line adjustmentunit to apply the first bit line voltage and the second bit linevoltage, may be in response to testing of the first and secondseparately-selectable sets of NAND strings. A select line adjustmentunit may be configured to apply a first select voltage to a first selectline in the first separately-selectable set of NAND strings and to applya second select voltage to a second select line in the secondseparately-selectable set of NAND strings. The first level of redundancyand the second level of redundancy may be determined according tocharacteristics of the first separately-selectable set of NAND stringsand the second separately-selectable set of NAND strings respectively.

An example of a method of operating a three dimensional nonvolatilememory that includes multiple separately-selectable sets of NAND stringsin a block, includes: measuring electrical current through aseparately-selectable set of NAND strings having a common select line;comparing the electrical current with predetermined criteria; if thecurrent does not meet the predetermined criteria then calculating one ormore bit line voltage offsets; and subsequently, adjusting bit linevoltages applied to bit lines connected to the separately-selectable setof NAND strings by the one or more bit line voltage offsets while otherbit line voltages applied to other separately-selectable sets of NANDstrings remain unadjusted.

The one or more bit line voltage offsets may be recorded for theseparately-selectable set of NAND strings. The one or more bit linevoltage offsets may be recorded in a table that contains a calculatedbit line voltage offset for each separately-selectable set of NANDstrings having a measured current that does not meet the predeterminedcriteria. An enhanced redundancy scheme may be applied to data stored insets of strings that do not meet the predetermined criteria, theenhanced redundancy scheme providing a higher degree of error correctioncapacity than a regular redundancy scheme that is applied to data storedin sets of strings that meet the predetermined criteria. Select gatethreshold voltage may be sensed for a select line in aseparately-selectable set of NAND strings; the select gate thresholdvoltage may be compared with a minimum threshold voltage; a select linevoltage offset may be calculated for a separately-selectable set of NANDstrings that have a select line threshold voltage less than the minimumthreshold voltage; and the select line voltage offset may be applied toselect line voltages that are subsequently applied to the select linewhen accessing the separately-selectable set of NAND strings.

The select line voltage offset may be recorded for theseparately-selectable set of NAND strings and additional select linevoltage offsets may be recorded for other separately-selectable sets ofNAND strings. Data to be stored in the separately-selectable set of NANDstrings may be encoded using an enhanced encoding scheme.

Various aspects, advantages, features and embodiments are included inthe following description of exemplary examples thereof, whichdescription should be taken in conjunction with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates schematically the main hardware components of amemory system.

FIG. 2 illustrates schematically a non-volatile memory cell.

FIG. 3 illustrates the relation between the source-drain current I_(D)and the control gate voltage V_(CG) for four different charges Q1-Q4that a floating gate may store.

FIG. 4A illustrates schematically a string of memory cells organizedinto a NAND string.

FIG. 4B illustrates an example of a NAND array 210 of memory cells,constituted from NAND strings 50 such as that shown in FIG. 4A.

FIG. 5 illustrates a page of memory cells, organized in the NANDconfiguration, being sensed or programmed in parallel.

FIGS. 6A-6C illustrate an example of programming a population of memorycells.

FIG. 7 shows an example of a physical structure of a 3-D NAND string.

FIG. 8 shows an example of a physical structure of a U-shaped 3-D NANDstring.

FIG. 9 shows an example of a cross section of a 3-D NAND memory arraywith U-shaped NAND strings in the y-z plane.

FIGS. 10A-C illustrate an example of a 3-D NAND memory with multipleseparately-selectable sets of strings in a block.

FIGS. 11A-B illustrate vertical NAND strings.

FIG. 12 illustrates a connection of a vertical NAND string with a commonsource.

FIG. 13 shows an example of a block with four separately-selectable setsof NAND strings.

FIGS. 14A-B show examples of a current measurement circuit.

FIG. 15 shows an example of a scheme for inspection and maintenance ofseparately-selectable sets of NAND strings.

FIG. 16 illustrates an example of a memory system.

DETAILED DESCRIPTION Memory System

Semiconductor memory devices include volatile memory devices, such asdynamic random access memory (“DRAM”) or static random access memory(“SRAM”) devices, non-volatile memory devices, such as resistive randomaccess memory (“ReRAM”), electrically erasable programmable read onlymemory (“EEPROM”), flash memory (which can also be considered a subsetof EEPROM), ferroelectric random access memory (“FRAM”), andmagnetoresistive random access memory (“MRAM”), and other semiconductorelements capable of storing information. Each type of memory device mayhave different configurations. For example, flash memory devices may beconfigured in a NAND or a NOR configuration.

The memory devices can be formed from passive and/or active elements, inany combinations. By way of non-limiting example, passive semiconductormemory elements include ReRAM device elements, which in some embodimentsinclude a resistivity switching storage element, such as an anti-fuse,phase change material, etc., and optionally a steering element, such asa diode, etc. Further by way of non-limiting example, activesemiconductor memory elements include EEPROM and flash memory deviceelements, which in some embodiments include elements containing a chargestorage region, such as a floating gate, conductive nanoparticles, or acharge storage dielectric material.

Multiple memory elements may be configured so that they are connected inseries or so that each element is individually accessible. By way ofnon-limiting example, flash memory devices in a NAND configuration (NANDmemory) typically contain memory elements connected in series. A NANDmemory array may be configured so that the array is composed of multiplestrings of memory in which a string is composed of multiple memoryelements sharing a single bit line and accessed as a group.Alternatively, memory elements may be configured so that each element isindividually accessible, e.g., a NOR memory array. NAND and NOR memoryconfigurations are exemplary, and memory elements may be otherwiseconfigured.

The semiconductor memory elements located within and/or over a substratemay be arranged in two or three dimensions, such as a two dimensionalmemory structure or a three dimensional memory structure.

In a two dimensional memory structure, the semiconductor memory elementsare arranged in a single plane or a single memory device level.Typically, in a two dimensional memory structure, memory elements arearranged in a plane (e.g., in an x-z direction plane) which extendssubstantially parallel to a major surface of a substrate that supportsthe memory elements. The substrate may be a wafer over or in which thelayer of the memory elements are formed or it may be a carrier substratewhich is attached to the memory elements after they are formed. As anon-limiting example, the substrate may include a semiconductor such assilicon.

The memory elements may be arranged in the single memory device level inan ordered array, such as in a plurality of rows and/or columns.However, the memory elements may be arrayed in non-regular ornon-orthogonal configurations. The memory elements may each have two ormore electrodes or contact lines, such as bit lines and word lines.

A three dimensional memory array is arranged so that memory elementsoccupy multiple planes or multiple memory device levels, thereby forminga structure in three dimensions (i.e., in the x, y and z directions,where the y direction is substantially perpendicular and the x and zdirections are substantially parallel to the major surface of thesubstrate).

As a non-limiting example, a three dimensional memory structure may bevertically arranged as a stack of multiple two dimensional memory devicelevels. As another non-limiting example, a three dimensional memoryarray may be arranged as multiple vertical columns (e.g., columnsextending substantially perpendicular to the major surface of thesubstrate, i.e., in the y direction) with each column having multiplememory elements in each column. The columns may be arranged in a twodimensional configuration, e.g., in an x-z plane, resulting in a threedimensional arrangement of memory elements with elements on multiplevertically stacked memory planes. Other configurations of memoryelements in three dimensions can also constitute a three dimensionalmemory array.

By way of non-limiting example, in a three dimensional NAND memoryarray, the memory elements may be coupled together to form a NAND stringwithin a single horizontal (e.g., x-z) memory device levels.Alternatively, the memory elements may be coupled together to form avertical NAND string that traverses across multiple horizontal memorydevice levels. Other three dimensional configurations can be envisionedwherein some NAND strings contain memory elements in a single memorylevel while other strings contain memory elements which span throughmultiple memory levels. Three dimensional memory arrays may also bedesigned in a NOR configuration and in a ReRAM configuration.

Typically, in a monolithic three dimensional memory array, one or morememory device levels are formed above a single substrate. Optionally,the monolithic three dimensional memory array may also have one or morememory layers at least partially within the single substrate. As anon-limiting example, the substrate may include a semiconductor such assilicon. In a monolithic three dimensional array, the layersconstituting each memory device level of the array are typically formedon the layers of the underlying memory device levels of the array.However, layers of adjacent memory device levels of a monolithic threedimensional memory array may be shared or have intervening layersbetween memory device levels.

Then again, two dimensional arrays may be formed separately and thenpackaged together to form a non-monolithic memory device having multiplelayers of memory. For example, non-monolithic stacked memories can beconstructed by forming memory levels on separate substrates and thenstacking the memory levels atop each other. The substrates may bethinned or removed from the memory device levels before stacking, but asthe memory device levels are initially formed over separate substrates,the resulting memory arrays are not monolithic three dimensional memoryarrays. Further, multiple two dimensional memory arrays or threedimensional memory arrays (monolithic or non-monolithic) may be formedon separate chips and then packaged together to form a stacked-chipmemory device.

Associated circuitry is typically required for operation of the memoryelements and for communication with the memory elements. As non-limitingexamples, memory devices may have circuitry used for controlling anddriving memory elements to accomplish functions such as programming andreading. This associated circuitry may be on the same substrate as thememory elements and/or on a separate substrate. For example, acontroller for memory read-write operations may be located on a separatecontroller chip and/or on the same substrate as the memory elements.

In other embodiments, types of memory other than the two dimensional andthree dimensional exemplary structures described here may be used.

FIG. 1 illustrates schematically the main hardware components of amemory system suitable for implementing some of the techniques describedhere. The memory system 90 typically operates with a host 80 through ahost interface. The memory system may be in the form of a removablememory such as a memory card, or may be in the form of an embeddedmemory system. The memory system 90 includes a memory 102 whoseoperations are controlled by a controller 100. The memory 102 comprisesone or more array of non-volatile memory cells distributed over one ormore integrated circuit chip. The controller 100 may include interfacecircuits 110, a processor 120, ROM (read-only-memory) 122, RAM (randomaccess memory) 130, programmable nonvolatile memory 124, and additionalcomponents. The controller is typically formed as an ASIC (applicationspecific integrated circuit) and the components included in such an ASICgenerally depend on the particular application. Memory systems may beused with a variety of hosts in a variety of different environments. Forexample, a host may be a mobile device such as a cell phone, laptop,music player (e.g. MP3 player), Global Positioning System (GPS) device,tablet computer, or the like. Such memory systems may be inactive,without power, for long periods during which they may be subject tovarious conditions including high temperatures, vibration,electromagnetic fields, etc. Memory systems for such hosts, whetherremovable or embedded, may be selected for low power consumption, highdata retention, and reliability in a wide range of environmentalconditions (e.g. a wide temperature range). Other hosts may bestationary. For example, servers used for internet applications may usenonvolatile memory systems for storage of data that is sent and receivedover the internet. Such systems may remain powered up withoutinterruption for extended periods (e.g. a year or more) and may befrequently accessed throughout such periods. Individual blocks may befrequently written and erased so that endurance may be a major concern.

Physical Memory Structure

FIG. 2 illustrates schematically a non-volatile memory cell. The memorycell 10 can be implemented by a field-effect transistor having a chargestorage unit 20, such as a floating gate or a charge trapping(dielectric) layer. The memory cell 10 also includes a source 14, adrain 16, and a control gate 30.

In practice, the memory state of a cell is usually read by sensing theconduction current across the source and drain electrodes of the cellwhen a reference voltage is applied to the control gate. Thus, for eachgiven charge on the floating gate of a cell, a corresponding conductioncurrent with respect to a fixed reference control gate voltage may bedetected. Similarly, the range of charge programmable onto the floatinggate defines a corresponding threshold voltage window or a correspondingconduction current window.

Alternatively, instead of detecting the conduction current among apartitioned current window, it is possible to set the threshold voltagefor a given memory state under test at the control gate and detect ifthe conduction current is lower or higher than a threshold current(cell-read reference current). In one implementation the detection ofthe conduction current relative to a threshold current is accomplishedby examining the rate the conduction current is discharging through thecapacitance of the bit line.

FIG. 3 illustrates the relation between the source-drain current I_(D)and the control gate voltage V_(CG) for four different charges Q1-Q4that the floating gate may be selectively storing at any one time. Withfixed drain voltage bias, the four solid I_(D) versus V_(CG) curvesrepresent four of seven possible charge levels that can be programmed ona floating gate of a memory cell, respectively corresponding to fourpossible memory states. As an example, the threshold voltage window of apopulation of cells may range from 0.5V to 3.5V. Seven possibleprogrammed memory states “0”, “1”, “2”, “3”, “4”, “5”, “6”, and anerased state (not shown) may be demarcated by partitioning the thresholdwindow into regions in intervals of 0.5V each. For example, if areference current, IREF of 2 μA is used as shown, then the cellprogrammed with Q1 may be considered to be in a memory state “1” sinceits curve intersects with I_(REF) in the region of the threshold windowdemarcated by VCG=0.5V and 1.0V. Similarly, Q4 is in a memory state “5”.

As can be seen from the description above, the more states a memory cellis made to store, the more finely divided is its threshold voltagewindow. For example, a memory device may have memory cells having athreshold voltage window that ranges from −1.5V to 5V. This provides amaximum width of 6.5V. If the memory cell is to store 16 states, eachstate may occupy from 200 mV to 300 mV in the threshold window. Thiswill require higher precision in programming and reading operations inorder to be able to achieve the required resolution.

NAND Structure

FIG. 4A illustrates schematically a string of memory cells organizedinto a NAND string. A NAND string 50 comprises a series of memorytransistors M1, M2, . . . Mn (e.g., n=4, 8, 16 or higher) daisy-chainedby their sources and drains. A pair of select transistors S1, S2controls the memory transistor chain's connection to the external worldvia the NAND string's source terminal 54 and drain terminal 56respectively. In a memory array, when the source select transistor S1 isturned on, the source terminal is coupled to a source line (see FIG.4B). Similarly, when the drain select transistor S2 is turned on, thedrain terminal of the NAND string is coupled to a bit line of the memoryarray. Each memory transistor 10 in the chain acts as a memory cell. Ithas a charge storage element 20 to store a given amount of charge so asto represent an intended memory state. A control gate 30 of each memorytransistor allows control over read and write operations. As will beseen in FIG. 4B, the control gates 30 of corresponding memorytransistors of a row of NAND string are all connected to the same wordline. Similarly, a control gate 32 of each of the select transistors S1,S2 provides control access to the NAND string via its source terminal 54and drain terminal 56 respectively. Likewise, the control gates 32 ofcorresponding select transistors of a row of NAND string are allconnected to the same select line.

When an addressed memory transistor 10 within a NAND string is read oris verified during programming, its control gate 30 is supplied with anappropriate voltage. At the same time, the rest of the non-addressedmemory transistors in the NAND string 50 are fully turned on byapplication of sufficient voltage on their control gates. In this way, aconductive path is effectively created from the source of the individualmemory transistor to the source terminal 54 of the NAND string andlikewise for the drain of the individual memory transistor to the drainterminal 56 of the cell.

FIG. 4B illustrates an example of a NAND array 210 of memory cells,constituted from NAND strings 50 such as that shown in FIG. 4A. Alongeach column of NAND strings, a bit line such as bit line 36 is coupledto the drain terminal 56 of each NAND string. Along each bank of NANDstrings, a source line such as source line 34 is coupled to the sourceterminals 54 of each NAND string. Also the control gates along a row ofmemory cells in a bank of NAND strings are connected to a word line suchas word line 42. The control gates along a row of select transistors ina bank of NAND strings are connected to a select line such as selectline 44. An entire row of memory cells in a bank of NAND strings can beaddressed by appropriate voltages on the word lines and select lines ofthe bank of NAND strings.

FIG. 5 illustrates a page of memory cells, organized in the NANDconfiguration, being sensed or programmed in parallel. FIG. 5essentially shows a bank of NAND strings 50 in the memory array 210 ofFIG. 4B, where the detail of each NAND string is shown explicitly as inFIG. 4A. A physical page, such as the page 60, is a group of memorycells enabled to be sensed or programmed in parallel. This isaccomplished by a corresponding page of sense amplifiers 212. The sensedresults are latched in a corresponding set of latches 214. Each senseamplifier can be coupled to a NAND string via a bit line. The page isenabled by the control gates of the cells of the page connected incommon to a word line 42 and each cell accessible by a sense amplifieraccessible via a bit line 36. As an example, when respectively sensingor programming the page of cells 60, a sensing voltage or a programmingvoltage is respectively applied to the common word line WL3 togetherwith appropriate voltages on the bit lines.

Physical Organization of the Memory

One difference between flash memory and other of types of memory is thata flash memory cell is generally programmed from the erased state. Thatis the floating gate is generally first emptied of charge. Programmingthen adds a desired amount of charge back to the floating gate. Flashmemory does not generally support removing a portion of the charge fromthe floating gate to go from a more programmed state to a lesser one.This means that updated data cannot overwrite existing data and isinstead written to a previous unwritten location.

Furthermore erasing is to empty all the charges from the floating gateand generally takes appreciable time. For that reason, it will becumbersome and very slow to erase cell by cell or even page by page. Inpractice, the array of memory cells is divided into a large number ofblocks of memory cells. As is common for flash EEPROM systems, the blockis the unit of erase. That is, each block contains the minimum number ofmemory cells that are erased together. While aggregating a large numberof cells in a block to be erased in parallel will improve eraseperformance, a large size block also entails dealing with a largernumber of update and obsolete data.

Each block is typically divided into a number of physical pages. Alogical page is a unit of programming or reading that contains a numberof bits equal to the number of cells in a physical page. In a memorythat stores one bit per cell (a Single Level Cell, or SLC” memory), onephysical page stores one logical page of data. In memories that storetwo bits per cell, a physical page stores two logical pages. The numberof logical pages stored in a physical page thus reflects the number ofbits stored per cell. The term Multi Level Cell, or “MLC” is generallyused to refer to memories that store more than one bit per cell,including memories that store three bits per cell (TLC), four bits percell, or more bits per cell. In one embodiment, the individual pages maybe divided into segments and the segments may contain the fewest numberof cells that are written at one time as a basic programming operation.One or more logical pages of data are typically stored in one row ofmemory cells. A page can store one or more sectors. A sector includesuser data and overhead data.

MLC Programming

FIG. 6A-6C illustrate an example of programming a population of 4-statememory cells. FIG. 6A illustrates the population of memory cellsprogrammable into four distinct distributions of threshold voltagesrespectively representing memory states “E”, “A”, “B” and “C”. FIG. 6Billustrates the initial distribution of “erased” threshold voltages foran erased memory. FIG. 6C illustrates an example of the memory aftermany of the memory cells have been programmed. Essentially, a cellinitially has an “erased” threshold voltage and programming will move itto a higher value into one of the three zones demarcated by verifylevels vV₁, vV₂ and vV₃. In this way, each memory cell can be programmedto one of the three programmed states “A”, “B” and “C” or remainun-programmed in the “erased” state. As the memory gets moreprogramming, the initial distribution of the “erased” state as shown inFIG. 6B will become narrower and the erased state is represented by the“0” state.

A 2-bit code having a lower bit and an upper bit can be used torepresent each of the four memory states. For example, the “E”, “A”, “B”and “C” states are respectively represented by “11”, “01”, “00” and“10”. The 2-bit data may be read from the memory by sensing in“full-sequence” mode where the two bits are sensed together by sensingrelative to the read demarcation threshold values rV₁, rV₂ and rV₃ inthree sub-passes respectively.

3-D NAND Structure

An alternative arrangement to a conventional two-dimensional (2-D) NANDarray is a three-dimensional (3-D) array. In contrast to 2-D NANDarrays, which are formed along a planar surface of a semiconductorwafer, 3-D arrays extend up from the wafer surface and generally includestacks, or columns, of memory cells extending upwards. Various 3-Darrangements are possible. In one arrangement a NAND string is formedvertically with one end (e.g. source) at the wafer surface and the otherend (e.g. drain) on top. In another arrangement a NAND string is formedin a U-shape so that both ends of the NAND string are accessible on top,thus facilitating connections between such strings.

FIG. 7 shows a first example of a NAND string 701 that extends in avertical direction, i.e. extending in the z-direction, perpendicular tothe x-y plane of the substrate. Memory cells are formed where a verticalbit line (local bit line) 703 passes through a word line (e.g. WL0, WL1,etc.). A charge trapping layer between the local bit line and the wordline stores charge, which affects the threshold voltage of thetransistor formed by the word line (gate) coupled to the vertical bitline (channel) that it encircles. Such memory cells may be formed byforming stacks of word lines and then etching memory holes where memorycells are to be formed. Memory holes are then lined with a chargetrapping layer and filled with a suitable local bit line/channelmaterial (with suitable dielectric layers for isolation).

As with planar NAND strings, select gates 705, 707, are located ateither end of the string to allow the NAND string to be selectivelyconnected to, or isolated from, external elements 709, 711. Suchexternal elements are generally conductive lines such as common sourcelines or bit lines that serve large numbers of NAND strings. VerticalNAND strings may be operated in a similar manner to planar NAND stringsand both Single Level Cell (SLC) and Multi Level Cell (MLC) operation ispossible. While FIG. 7 shows an example of a NAND string that has 32cells (0-31) connected in series, the number of cells in a NAND stringmay be any suitable number. Not all cells are shown for clarity. It willbe understood that additional cells are formed where word lines 3-29(not shown) intersect the local vertical bit line.

FIG. 8 shows a second example of a NAND string 815 that extends in avertical direction (z-direction). In this case, NAND string 815 forms aU-shape, connecting with external elements (source line “SL” and bitline “BL”) located on the top of the structure. At the bottom of NANDstring 815 is a controllable gate (back gate “BG”) which connects thetwo wings 816A, 816B of NAND string 815. A total of 64 cells are formedwhere word lines WL0-WL63 intersect the vertical local bit line 817(though in other examples other numbers of cells may be provided).Select gates SGS, SGD, are located at either end of NAND string 815 tocontrol connection/isolation of NAND string 815.

Vertical NAND strings may be arranged to form a 3-D NAND array invarious ways. FIG. 9 shows an example where multiple U-shaped NANDstrings in a block are connected to a bit line. In this case, there aren separately-selectable sets of strings (Sting 1-String n) in a blockconnected to a bit line (“BL”). The value of “n” may be any suitablenumber, for example, 8, 12, 16, 32, or more. Strings alternate inorientation with odd numbered strings having their source connection onthe left, and even numbered strings having their source on the right.This arrangement is convenient but is not essential and other patternsare also possible.

Common source lines “SL” connect to one end of each NAND string(opposite to the end that connects to the bit line). This may beconsidered the source end of the NAND string, with the bit line endbeing considered as the drain end of the NAND string. Common sourcelines may be connected so that all source lines for a block may becontrolled together by a peripheral circuit. Thus, NAND strings of ablock extend in parallel between bit lines on one end, and common sourcelines on the other end.

FIG. 10A shows a memory structure, in cross section along the bit linedirection (along y-direction) in which straight vertical NAND stringsextend from common source connections in or near a substrate to globalbit lines (GBL0-GBL3) that extend over the physical levels of memorycells. Word lines in a given physical level in a block are formed from asheet of conductive material. Memory hole structures extend down throughthese sheets of conductive material to form memory cells that areconnected in series vertically (along the z-direction) by vertical bitlines (BL0-BL3) to form vertical NAND strings. Within a given blockthere are multiple NAND strings connected to a given global bit line(e.g. GBL0 connects with multiple BL0s). NAND strings are grouped intosets of strings that share common select lines. Thus, for example, NANDstrings that are selected by source select line SGS0 and drain selectline SGD0 may be considered as a set of NAND strings and may bedesignated as String 0, while NAND strings that are selected by sourceselect line SGS1 and drain select line SGD1 may be considered as anotherset of NAND strings and may be designated as String 1 as shown. A blockmay consist of any suitable number of such separately-selectable sets ofstrings. It will be understood that FIG. 10A shows only portions ofGBL0-GBL3, and that these bit lines extend further in the y-directionand may connect with additional NAND strings in the block and in otherblocks. Furthermore, additional bit lines extend parallel to GBL0-GBL3(e.g. at different locations along x-axis, in front of, or behind thelocation of the cross-section of FIG. 10A).

FIG. 10B illustrates separately-selectable sets of NAND strings of FIG.10A schematically. It can be seen that each of the global bit lines(GBL0-GBL3) is connected to multiple separately selectable sets of NANDstrings (e.g. GBL0 connects to vertical bit line BL0 of String 0 andalso connects to vertical bit line BL0 of String 1) in the portion ofthe block shown. In some cases, word lines of all strings of a block areelectrically connected, e.g. WL0 in string 0 may be connected to WL0 ofString 1, String 2, etc. Such word lines may be formed as a continuoussheet of conductive material that extends through all sets of strings ofthe block. Source lines may also be common for all strings of a block.For example, a portion of a substrate may be doped to form a continuousconductive region underlying a block that is isolated from similarconductive regions underlying other blocks thus allowing separatebiasing to erase a block as a unit. Source and drain select lines arenot shared by different sets of strings so that, for example, SGD0 andSGS0 can be biased to select String 0 without similarly biasing SGD1 andSGS1. Thus, String 0 may be individually selected (connected to globalbit lines and a common source) while String 1 (and other sets ofstrings) remain isolated from global bit lines and the common source.Accessing memory cells in a block during programming and readingoperations generally includes applying select voltages to a pair ofselect lines (e.g. SGS0 and SGD0) while supplying unselect voltages toall other select lines of the block (e.g. SGS1 and SGD1). Then,appropriate voltages are applied to word lines of the block so that aparticular word line in the selected set of strings may be accessed(e.g. a read voltage is applied to the particular word line, whileread-pass voltages are applied to other word lines). Erasing operationsmay be applied on an entire block (all sets of strings in a block)rather than on a particular set of strings in a block.

FIG. 10C shows a separately selectable set of NAND strings, String 0, ofFIGS. 10A-B in cross section along the X-Z plane. It can be seen thateach global bit line (GBL0-GBLm) is connected to one vertical NANDstring (vertical bit line BL0-BLm) in String 0. String 0 may be selectedby applying appropriate voltages to select lines SGD0 and SGS0. Othersets of strings are similarly connected to global bit lines (GBL0-GBLm)at different locations along the Y direction and with different selectlines that may receive unselect voltages when String 0 is selected.

Bad Blocks, Bad Columns, Bad Rows

In some memory systems, bad blocks are detected and are marked so thatthey are not subsequently used for storage of user data. For example,detection and marking of bad blocks may be performed during factorytesting. A bad block may be a block that fails to meet a set of criteriarelated to, for example, reading, writing, and/or erasing (e.g. failingto read, write, or erase within time limit), having an excessively higherror rate or an excessive number of bad cells, and/or other criteria.If a particular die has more than a threshold number of bad blocks thenthe die may be discarded. In some cases, dies may be classifiedaccording to the number of bad blocks that they contain. Generally, dieswith fewer bad blocks are preferable because data storage capacity ofthe memory is reduced by the number of bad blocks.

In some cases, blocks may have some inoperable components while othercomponents remain operable. For example, one or more column in a blockmay be found to be inoperable and may be replaced by a spare column.Similarly, one or more rows of memory cells may be replaced in somecases. Small numbers of bad cells may be acceptable if the error ratesresulting from such bad cells are low enough to allow correction byError Correction Code (ECC) or some other form of redundancy.

In an example, blocks with multiple separately-selectable sets ofstrings that are identified as “bad” blocks are further tested todetermine if there are operable sets of strings in the blocks (e.g. somesets of strings may meet test criteria even though the bock as a wholedoes not meet the criteria). While some failure modes may result in badblocks that have no operable cells, other failure modes may affect aparticular portion of a block and may leave at least some operablememory cells. Some failure modes may affect individualseparately-selectable sets of NAND strings within a block while othersets of NAND strings remain operable. Testing of blocks identified as“bad” blocks may identify a number of blocks that contain a mix ofoperable and inoperable portions. In some cases, such partially-badblocks may subsequently be used to store data thereby increasing thecapacity of the memory. In some cases, portions of blocks that fail tomeet testing criteria may be reconfigured so that that they meet thetesting criteria. For example, a portion of a memory that fails testingwhen default operating parameters are used may pass when some modifiedoperating parameters are used.

One failure mode may be encountered when a block or a portion of a blockfails to erase. Such erase fails may be detected during testing or aftersome significant use (e.g. after a block has been used to store userdata for a period of time). In general, after a block is subject to anerase step, an erase-verify step is used to determine if memory cellsare in the erased condition, or if further erasing is needed. While anerase step may apply erase conditions to all memory cells of a block sothat the block is erased as a unit, erase-verify may be applied to aportion of the block. For example, one separately-selectable set of NANDstrings in a block may be selected for erase-verify at a time. Byapplying appropriate select and deselect voltages to select lines of ablock, a particular set of NAND strings may be selected while other setsof NAND strings are deselected. Appropriate erase-verify voltages may beapplied to all word lines so that all cells are turned on, which shouldallow current flow through NAND strings. This current may be measured todetermine if the memory cells are erased. If the number of NAND stringsin a selected set of NAND strings that are not adequately erased (e.g.that do not have a current greater than a minimum current) is greaterthan a maximum allowable number then another erase step may beperformed, followed by another erase-verify step. In general, erase anderase-verify steps are repeated until a maximum time or a maximum numberof cycles is reached. When such a maximum is reached an erase failuremay be reported and the set of NAND strings may be considered bad (andthe block may be considered a bad block in some cases).

In some cases, erase failure occurs because memory cells fail to erase(remain programmed) even after a number of erase cycles. In other cases,an erase failure may occur for other reasons. A NAND string may fail anerase-verify step even though memory cells are adequately erased. Forexample, current through a NAND string may remain low because of somecomponent other than a memory cell contributes significantly to theresistance of the NAND string causing current through the NAND string toremain below a minimum current. For example, select transistors maycontribute significant resistance in some cases. In some cases,connections at ends of NAND strings may contribute significantresistance. For example, there may be poor connections where NANDstrings connect to a common source or to global bit lines, which mayprovide a relatively high resistance that reduces current flow through aNAND string.

FIG. 11A illustrates a portion of a 3-D block of NAND strings includingseparately-selectable sets of NAND strings. Metal contacts (e.g. contact150) extend between drain select transistors (select gate “SG”) andglobal bit lines (“GBL”). In some cases, these contacts may have higherresistance than normal, e.g. because of process related variation, whichmay result in lower current through the corresponding NAND string.

FIG. 11B illustrates an individual NAND string of FIG. 11B including itsconnection to a corresponding global bit line (“GBL”) and its sourceconnection through the underlying substrate and through a verticalconductor, or Local Interconnect (“LI”) that connects the source line inthe substrate with the memory's source terminal. Resistance at any pointalong the current path shown may result in low current through the NANDstring. For example, resistance at the top of the NAND string where itconnects to the global bit line (GBL) at contact 150, at the bottom ofthe NAND string where it connects to the source area in the substrate,or where the source area in the substrate connects with the verticalcommon source connection (LI). Resistance may also result from defectiveselect transistors (either source select transistors or drain selecttransistors), or defective dummy cells. Increased resistance may bespecific to an individual NAND string, e.g. resistance due to a poorconnection between the NAND string and a global bit line. Increasedresistance may be common to multiple NAND strings, e.g. resistance dueto a poor connection between the source area in the substrate and avertical common source connection may affect an entireseparately-selectable set of NAND strings.

FIG. 12 illustrates an example of memory holes (“MH”) connecting to acommon source area 154 in a substrate. Current flows through verticalLocal Interconnect (“LI”) that is formed in a source terminal (“ST”),through an N+ doped area, common source area 154, and through thechannels of vertical NAND strings formed in the memory holes. Currentflow through a given memory hole is controlled by select transistors,e.g. source select transistors 156 shown. Dummy word lines (“DWL”)control dummy memory cells which are connected in series with memorycells that store user data.

Low Bit Line Current

FIG. 13 illustrates four separately-selectable sets of NAND strings of ablock, Strings 0-3, schematically. An example of an operation to reclaimbad portions of such a block may be directed to one set of NAND stringsat a time and may apply different solutions to different sets of NANDstrings. For example, when a block fails to erase (e.g. erase-verifyindicates a number of NAND strings with unacceptably low current thatexceeds a maximum number) then the cause of such low current flow may beinvestigated by individually testing sets of NAND strings. During suchtesting, the set of string is selected by applying appropriate selectline voltages while other select lines of the same block receiveunselect voltages. A read operation may proceed word line by word lineto determine if memory cells are in the erased state. Where current flowthrough a NAND string is low, and all, or substantially all, of thememory cells are erased, this generally indicates that the low currentis caused by another element, such as resistance of another component.By identifying such resistance, an appropriate solution may beidentified and applied so that the NAND string may be reclaimed andsubsequently used to store data.

In some cases, low current flow through NAND strings may be overcome byapplying higher bit line voltage. Where a default bit line voltage failsto generate a required current flow due to some resistance, an increasedbit line voltage may be enough to provide the required current flowaccording to the equation V=I/R. Thus, one solution may include applyinga higher bit line voltage to the global bit line of a NAND string thathas low current flow. This may be done on a bit line by bit line basiswhere a relatively small number (e.g. fewer than a threshold number) ofNAND strings in a separately-selectable set of NAND strings have lowcurrent flow. In some memory systems, bit lines are grouped intocolumns, where a column may include, for example, 8, 16, 32 or more bitlines. Higher bit line voltage may be applied on a column by columnbasis. In some cases, where a relatively large number of NAND strings(e.g. greater than a threshold number) in a separately-selectable set ofNAND strings have low flow, then increased bit line voltage may beapplied to all NAND strings in the set of NAND strings. A record may bemaintained to indicate that modified bit line voltages are to be appliedwhen accessing a separately-selectable set of NAND stings. A singleincreased bit line voltage may be used throughout such a set, ordifferent increased bit line voltages may be used for different columnsor for individual NAND strings, e.g. a set of different bit line voltageoffsets may be obtained to adjust different bit line voltages to provideadequate current. A record may have a single entry for a set ofseparately-selectable NAND strings or may have an entry for a column,which may include multiple bit lines, or may have individual entries forbit lines that require increased voltage. Entries may be one-bit entriesthat indicate an increased bit line voltage, or may be larger entriesthat indicate the magnitude of an increased bit line voltage.

FIGS. 14A-B shows an example of a circuit for testing NAND strings. Whenmemory cells in a separately-selectable set of NAND strings are read andconfirmed as being erased, this circuit may be used to measure currentand to identify an increased bit line voltage that may provide adequatecurrent through a NAND string. The resistance 401 shown in this circuitdiagram is the component being tested and may include one or more NANDstrings (with memory cells turned on) along with components connected inseries with the NAND string. A digital to analog converter (DAC)controls the gate of a transistor connected to a fixed voltage (2 voltsin this example) to control the current through the NAND string. Acomparator 405 compares the voltage at the input node 403 with apredetermined voltage (0.5*VCCQ, or 1 volt, in the example of FIG. 14A).If the voltage at the input node exceeds one volt, then the currentthrough the NAND string is below the pass/fail boundary. By modifyingthe voltage applied to the input node 403 through the transistor, anappropriate voltage may be found that provides adequate current throughthe NAND string. The resistance of a NAND string may be obtained byfinding the voltage of the input node when applying a fixed current sothat an appropriate voltage can be applied to generate the requiredcurrent. For example, a NAND string may have a resistance of fivehundred to a thousand kilo Ohms (500 kΩ to 1MΩ). Higher resistance NANDstrings may receive a bit line voltage that is increased to compensatefor the increased resistance (i.e. for a given value of R, some value ofV may produce adequate current according to I=V/R).

Testing may be performed under different conditions and test results maybe compared with various criteria including current flow under differentconditions. For example, as shown in FIG. 14B, low power testing mayapply a relatively low current, so that the expected voltage at theinput node is correspondingly less, and the comparator voltage isreduced (to 0.25VCCQ, or 0.5 volts, in this example). Testing differentconditions may allow bit line voltage offsets to be used more precisely.For example, a bit line voltage offset may be used for some operationsbut not for others. For example, a bit line voltage offset may be usedfor erasing (relatively high current) but may not be used for reading(relatively low current). An appropriate testing scheme may be appliedaccording to the currents that are used when accessing the memory (i.e.currents used in erase, read, and write operations).

In some cases, increased NAND string resistance may be caused by selecttransistors. Generally, because select lines are shared by all NANDstrings in a separately-selectable set of NAND strings, select lineissues may affect most or all NAND strings of a separately-selectableset of NAND strings. In an example, a set of NAND strings that shows ahigh number of NAND strings with low current (high resistance) is testedto see if higher select line voltage may overcome the problem. Increasedselect line voltages may be tested to see if the number of highresistance NAND strings can be reduced to an acceptable number. Ifincreased select line voltage reduces the number of high resistance NANDstrings sufficiently, then this indicates that select transistors are asubstantial cause of resistance. Subsequently, access to the set of NANDstrings may use an increased select line voltage for at least one selectline. A record may be maintained to indicate that an increased selectline voltage is required for this separately-selectable set of NANDstrings and subsequent access operations may use the increased selectline voltage accordingly. In some cases, a single increased select linevoltage may be used for any separately-selectable set of NAND stringsthat can be fixed in this way. In other cases, select line voltage maybe increased by different amounts according to results of testing. Itmay be preferable to use lower select line voltages where possible sothat a range of select line voltages may be applied depending on theseverity of the problem encountered in different separately-selectablesets of NAND strings.

In some cases, a portion of a block may be reclaimed by combiningapproaches, e.g. by applying increased select line voltage andincreasing bit line voltage. It will be understood that these approachesare not exclusive and may be applied in any manner that is effectiveincluding by combining with other approaches.

In some examples, where a portion of a block is suspected of beingdefective in some way, additional steps may be taken to protect the datastored in such a portion. For example, a higher level of redundancy maybe applied to data stored in such a portion than other portions. Amemory system that encodes data using a default encoding scheme with acertain error correction capacity may encode data for storage in asuspect area with an enhanced encoding scheme what has a higher errorcorrection capacity. For example, a first error correction code (ECC)scheme may be applied as a default scheme to data stored in the memoryarray, while a second ECC scheme with a higher redundancy ratio (andthus greater error correction capacity) may be applied to data stored insuspect areas. In some cases an additional redundancy scheme may beapplied to data stored in suspect portions. For example, in addition toa default ECC scheme, another redundancy scheme may be added toparticular portions of data. An example of such an additional scheme isan exclusive OR (XOR) scheme that is applied to a number of portions ofdata, and which allows one of the portions to be recalculated from theother portions and the redundancy data. An increased redundancy ratiomay be the result of an enhanced redundancy scheme or of an additionalredundancy scheme that is selectively applied to data in suspect areas.

An area may be considered suspect and data stored in the area may besubject to additional measures for a number of reasons. Where a portionof a block, such as a separately-selectable set of NAND strings, failsto meet some criteria such as having a high number of NAND strings withlow current flow, the portion may be considered suspect. A higher thanusual select line voltage may be used and/or a higher than usual bitline voltage may be applied and/or a higher redundancy ratio may beapplied to stored data. A table may be maintained that indicates whichportions of a block should have data encoded with an increasedredundancy ratio. In some cases, such a table may be combined with atable that indicates other operating parameters such as increased bitline voltage and/or increased select line voltage. Where a blockcontains suspect portions, access time may be increased, e.g. because ofadditional encoding and configuration time, and the risk of data lossmay be higher. Therefore, such blocks may be maintained as reserveblocks that are only used when there are no good blocks available. Thus,user data may only be stored in such blocks after all good blocks areused so that performance is not affected.

FIG. 15 illustrates an example of a scheme that inspects portions of athree dimensional NAND block and applies certain maintenance stepsaccordingly. In an inspection routine directed to memory holeconnectivity, the conductivity of a memory hole (“MH”) is checked 501 bymeasuring conductivity of the memory hole 503 after memory cells arechecked to ensure they are adequately erased. If the memory hole has alow current (high resistance) then a memory hole problem is confirmed505 and finger maintenance is initiated 507 (the term “finger” may beapplied to a separately-selectable set of NAND strings which extend inparallel like a set of fingers). In another inspection routine, thethreshold voltage (V_(T)) distributions of the select gates aredetermined 511 and compared with a target threshold voltage range 513 toidentify problems. Alternatively, the number of logic 1 and logic 0 bitsread may be counted (e.g. by a Direct Memory Counter “DMC”) to identifyselect transistors that have problems. If the number of bad strings(strings with select gates having threshold voltages outside the desiredrange) is not greater than a threshold 515 then the portion of the blockmay be considered normal and may be operated with default operatingparameters 517. If the number of bad strings exceeds the thresholdnumber 515 then this separately-selectable set of NAND strings may beconsidered suspect and may be compared with a list of suspect sets forfinger maintenance 519. If the finger is not on the list, then it isadded to the list 521. During finger maintenance 507, one or moremodified operating parameters may be calculated for aseparately-selectable set of strings, such as increased bit linevoltage, increased select line voltage, increased redundancy ratio, orother parameters.

Subsequently, when the finger is accessed, a determination is made as towhether the access is a program operation 525. If it is a programoperation then conditions are adjusted 527 for the word line (WL) beingprogrammed, e.g. by increasing one or more select line voltages and/orincreasing one or more bit line voltages and/or applying a higherredundancy ratio to the data being stored by providing additional paritydata in the finger 531.

If the operation is not a program operation, then a determination ismade as to whether it is a host read operation 535. If it is a host readoperation then select gate (SG) and/or bit line (BL) voltages may beadjusted 537 to perform the read. Adjustment may be indicated by arecord entry. After data is read and returned to the host, data may berelocated 539 to a safer location (e.g. a finger that does not requireadjusted voltages).

If the operation is not a program or host write operation then adetermination is made as to whether it is an erase operation 545. If itis an erase operation then select gate (SG) and/or bit line (BL)voltages may be adjusted 547. Adjustment may be indicated by a recordentry. The erase operation then proceeds 549 with the adjusted voltages.

If the operation is not a program, host write, or erase operation, thena read scrub operation is performed 555 that measures the health of thefinger, e.g. measures the number of cells that have some level ofdisturbance and may measure the amount of disturbance. Read scrub may beperformed with modified parameters such as select line voltages and bitline voltages. The data is relocated 557 to another location (using ECCto correct any errors in the data).

FIG. 16 shows an example of components of a memory system 601 connectedto host 80. Memory system 601 includes memory controller 603 and memorydie 605 (and additional memory dies). Memory die 605 includes a numberof individually-erasable 3-D NAND flash memory blocks. Each block hasmultiple separately-selectable sets of NAND strings. Some blocks areidentified as bad blocks (“BAD”) and are not used. Some blocks have atleast one separately-selectable set of NAND strings that does not meetsome criteria (e.g. block 607 contains four separately-selectable setsof NAND strings with string 609 failing to meet some criteria). Memorydie 605 also includes bit line driver 611, which is configurable toapply different bit line voltages when accessing differentseparately-selectable sets of NAND strings (e.g. applying a higher bitline voltage when accessing string 609). Bit line sensing unit 613 isconfigured to sense bit line current and compare bit line current with athreshold current. Select line sensing unit 615 is configured to senseselect line threshold voltage and to compare it with a minimum thresholdvoltage. Memory controller 603 includes a programming circuit 617, areading circuit 619, and an erase circuit 621 which may control accessto memory die 605 in combination with peripheral circuits in memory die605. A bit line voltage (VBL) adjustment unit 623 is configured to applydifferent bit line voltages to different separately-selectable sets ofNAND strings (in combination with bit line driver 611). Bit line voltageadjustment unit 623 is in communication with a bit line voltage table625, which records bit line voltages (or offsets) to be used whenaccessing different separately-selectable NAND strings. A select gatevoltage (VSG) adjustment unit 627 is configured to apply differentselect line voltages to different separately-selectable sets of NANDstrings in a block (e.g. applying higher select line voltage to string609 than other strings of block 607) in combination with peripheralcircuits in memory die 605. Select gate voltage adjustment unit 627 isin communication with select gate voltage table 629, which recordsdifferent select gate voltages (or offsets) for different sets ofstrings. Adaptive redundancy unit 631 is configured to apply differentredundancy ratios to data stored in different areas of a memory block(e.g. higher redundancy ratio to data stored in separately-selectableset of NAND strings 609 than other sets in block 607). An adaptiveredundancy unit may include an ECC engine with variable redundancy. Anadaptive redundancy unit may include different components to applydifferent schemes (e.g. an ECC engine and an XOR circuit). Adaptiveredundancy unit 631 is in communication with redundancy table 633, whichrecords redundancy ratios to be used for data stored in differentportions of a block.

CONCLUSION

The foregoing detailed description has been presented for purposes ofillustration and description. It is not intended to be exhaustive or tolimit the attached claims. Many modifications and variations arepossible in light of the above teaching.

It is claimed:
 1. A nonvolatile memory system comprising: a block thatcontains a plurality of separately-selectable sets of memory units; abit line current sensing unit that is configured to sense bit linecurrent for a separately-selectable set of memory units of the block andto compare the bit line current to a minimum current; and a bit linevoltage adjustment unit that is in communication with the bit linecurrent sensing unit, the bit line voltage adjustment unit configured toapply a first bit line voltage to separately-selectable sets of memoryunits that have bit line currents greater than the minimum current, andconfigured to apply a second bit line voltage to separately-selectablesets of memory units that have bit line currents less than the minimumcurrent, the second bit line voltage being greater than the first bitline voltage.